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LPC2880; LPC2888
16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
Rev. 01 -- 22 June 2006 Preliminary data sheet
1. General description
The LPC2880/LPC2888 are an ARM7-based microcontroller for portable applications requiring low power and high performance. It includes a USB 2.0 Hi-Speed device interface, an external memory interface that can interface to SDRAM and flash, an SD/MMC memory card interface, A/D and D/A converters, and serial interfaces including UART, I2C-bus, and I2S-bus. Architectural enhancements like multi-channel DMA, processor cache, simultaneous operations on multiple internal buses, and flexible clock generation help ensure that the LPC2880/LPC2888 can handle more demanding applications than many competing devices. The chip can be powered from a single battery, from the USB, or from regulated 1.8 V and 3.3 V.
2. Features
2.1 Key features
I I I I I I I I I I I ARM7TDMI processor with 8 kB cache, operating at up to 60 MHz 1 MB on-chip flash program memory with 128-bit access for high performance 64 kB SRAM Boot ROM allows execution of flash code, external code, or flash programming via USB On-chip DC-to-DC converter can generate all required voltages from a single battery or from USB power Multiple internal buses allow simultaneous simple DMA, USB DMA, and program execution from on-chip flash without contention External memory controller supports flash, SRAM, ROM, and SDRAM Advanced Vectored Interrupt Controller, supporting up to 30 vectored interrupts Innovative Event Router allows interrupt, power-up, and clock-start capabilities from up to 107 sources Multi-channel GP DMA controller that can be used with most on-chip peripherals as well as for memory-to-memory transfers Serial interfaces: N Hi-Speed USB 2.0 device (480 Mbit/s or 12 Mbit/s) with on-chip physical layer N UART with fractional baud rate generation, flow control, IrDA support, and FIFOs N I2C-bus interface N I2S-bus (Inter IC Sound bus) interface for independent stereo digital audio input and output SD/MMC memory card interface 10-bit A/D converter with 5-channel input multiplexing
I I
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
I I I I I I
16-bit stereo A/D and D/A converters with amplification and gain control Advanced clock generation and power control reduce power consumption Two 32-bit timers with selectable prescalers 8-bit/4-bit LCD interface bus Real Time Clock can be clocked by 32 kHz oscillator or another source Watchdog Timer with interrupt and/or reset capabilities.
3. Ordering information
Table 1. Ordering information Package Name LPC2880FET180 LPC2888FET180 TFBGA180 TFBGA180 Description Version plastic thin fine-pitch ball grid array package; 180 SOT640-1 balls; body 10 x 10 x 0.8 mm plastic thin fine-pitch ball grid array package; 180 SOT640-1 balls; body 10 x 10 x 0.8 mm Type number
3.1 Ordering options
Table 2. Ordering options Flash memory 1 MB RAM 64 kB 64 kB Temperature range -40 C to +85 C -40 C to +85 C Type number LPC2880FET180 LPC2888FET180
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
2 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
4. Block diagram
JTAG_TRST
JTAG_TMS
JTAG_TDO
JTAG_TCK
JTAG_SEL
JTAG_TDI
A[20:0], D[15:0], etc.
DP, DM, VBUS, RREF, RPU
LPC2880/2888
JTAG DEBUG INTERFACE 1 MB FLASH(1) FLASH INTERFACE 64 kB SRAM SRAM INTERFACE BOOT ROM ROM INTERFACE ARM7TDMI-S 8 kB CACHE
EXTERNAL MEMORY CONTROLLER
HS USB WITH DMA
VECTORED INTERRUPT CONTROLLER
MULTI-LAYER AHB +1.5 V or +5 V 3.3 V, 1.8 V START, STOP WATCHDOG TIMER SYSTEM CONTROL EVENT ROUTER XTALI XTALO X32I X32O Px.y CLOCK OSCILLATOR GENERATION AND PLLs UNIT OSCILLATOR REAL-TIME CLOCK GENERAL PURPOSE I/O 10-BIT A/D CONVERTER I2C-BUS INTERFACE 32-BIT TIMER 0 32-BIT TIMER 1 AHB TO APB BRIDGE 3 DC-TO-DC CONVERTER AHB TO APB BRIDGE 0 AHB TO APB BRIDGE 1 AHB TO APB BRIDGE 2 GP DMA CONTROLLER register interface
SD/MMC CARD INTERFACE UART WITH IrDA LCD INTERFACE
MCLK, MCMD MD[3:0] TXD, RTS RXD, CTS LCD bus
SCL, SDA
AIN[4:0] VREF, AIN_LNA, AINA, AINB AOUT_LNA
TRIPLE ANALOG FIFO INPUT DUAL ANALOG OUTPUT
FIFO
I2S-BUS INPUT I2S-BUS OUTPUT
DATI BCKI, WSI DATO BCKO, DCLKO, WSO
002aac296
AOUTA, AOUTA_DAC, AOUTB, AOUTB_DAC
FIFO
FIFO
(1) LPC2888 only.
Fig 1. Block diagram
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
3 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
5. Pinning information
5.1 Pinning
ball A1 index area 1 A B C D E F G H J K L M N P R T U V
002aac239
2 3
4 5
6 7
8 9
10 12 14 16 18 11 13 15 17
LPC2880/ LPC2888
Transparent top view
Fig 2. Pin configuration Table 3. Pin 1 5 9 13 17 1 5 9 13 17 1 5 9 13 17 1
LPC2880_LPC2888_1
Pin allocation table Pin 2 6 10 14 18 2 6 10 14 18 2 6 10 14 18 2 Symbol D1/P0[1] VSS2(EMC) MCLKO/P1[14] A15/P0[31] A6/P0[22] D2/P0[2] D11/P0[11] CKE/P1[9] A16/P1[0] A7/P0[23] LD0/P4[4] D10/P0[10] CAS/P1[16] A17/P1[1] A8/P0[24] LD3/P4[7] 3 3 7 11 15 3 7 11 15 Pin 3 7 11 15 Symbol D3/P0[3] VDD2(EMC) DQM1/P1[11] VSS1(EMC) LCS/P4[0] D13/P0[13] STCS2/P1[5] A13/P0[29] LD2/P4[6] D12/P0[12] WE/P1[15] A14/P0[30] LD5/P4[9] 4 4 8 12 16 4 8 12 16 Pin 4 8 12 16 Symbol D4/P0[4] STCS1/P1[5] BLS0/P1[12] VDD1(EMC) D5/P0[5] D15/P0[15] BLS1/P1[13] A11/P0[27] D8/P0[8] D14/P0[14] DQM0/P1[10] A12/P0[28] -
Symbol D0/P0[0] D6/P0[6] RAS/P1[17] A18/P1[2] OE/P1[18] RPO/P1[19] D7/P0[7] DYCS/P1[8] A19/P1[3] A9/P0[25] LD1/P4[5] D9/P0[9] STCS0/P1[5] A20/P1[4] A10/P0[26] LD4/P4[8]
Row A
Row B
Row C
Row D
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
4 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Pin allocation table ...continued Pin 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 18 2 14 Symbol A5/P0[21] LD6/P4[10] A2/P0[18] LER/P4[3] WSO LRW/P4[2] BCKO/P3[5] MCMD/P5[1] VSS4(IO) MD1/P5[4] VDD4(IO3V3) CTS/P6[2] MODE1/P2[2] VREFP(DAC) STOP AOUTA_DAC DCDC_CLEAN AOUTRA DCDC_VDDO(1V8) VSS1(AMP) 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 3 15 Pin 15 Symbol LD7/P4[11] LRS/P4[1] MCLK/P5[0] MD0/P5[5] MD3/P5[2] RXD/P6[0] TXD/P6[1] AOUTB_DAC AOUTA AOUTB 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 4 16 Pin 16 Symbol A3/P0[19] A0/P0[16] DCLKO/P3[3] DATI/P3[0] SCL MODE2/P2[3] P2[0] DCDC_GND DCDC_VDDI(3V3) DCDC_VSS2 RREF
Table 3. Pin 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13 17 1 13
LPC2880_LPC2888_1
Symbol A4/P0[20] VDD1(IO3V3) A1/P0[17] VSS1(IO) DATO/P3[6] VSS1(CORE) WSI/P3[2] VDD1(CORE1V8) BCKI/P3[1] MD2/P5[3] SDA RTS/P6[3] P2[1] VDD(DAC3V3) START VREFN(DAC) DCDC_VBAT AOUTRB DCDC_LX2 VSS2(AMP) -
Row E
Row F
Row G
Row H
Row J
Row K
Row L
Row M
Row N
Row P
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
5 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Pin allocation table ...continued Pin 18 2 14 18 2 6 10 14 18 2 6 10 14 18 2 6 10 14 18 Symbol DCDC_VSS1 VDD2(AMP3V3) DCDC_VDDO(3V3) AOUT_LNA AIN3 XTALI RESET DCDC_VUSB VREFP(DADC) AIN2 VSS(ADC) VBUS/P7[0] VDD3(USB3V3) VSS(DADC) VSS2(IO) VDD(ADC3V3) VDD3(IO3V3) VDD4(USB3V3) 3 7 11 15 3 7 11 15 3 7 11 15 3 15 Pin Symbol AIN_LNA VCOM(DADC) AIN1 VSS3(INT) RPU VDD(DADC3V3) AIN0 VSS2(INT) VDD1(USB1V8) VDD(DADC1V8) X32I VDD2(CORE1V8) VDD1(FLASH1V8) 4 8 12 16 4 8 12 16 4 8 12 16 4 16 Pin Symbol VSS2(USB) AINA X32O VSS1(INT) VSS3(USB) JTAG_SEL VDD(OSC321V8) JTAG_TMS VDD2(USB1V8) JTAG_TCK VSS(OSC32) VSS2(CORE) VDD2(FLASH1V8) -
Table 3. Pin 17 1 13 17 1 5 9 13 17 1 5 9 13 17 1 5 9 13 17
Symbol DCDC_LX1 VDD1(AMP3V3) VSS1(USB) AINB JTAG_TDI VSS(OSC) JTAG_TRST DM VREF(DADC) AIN4 VDD(OSC1V8) JTAG_TDO DP VREFN(DADC) VDD2(IO3V3) XTALO VSS3(IO) VSS3(CORE)
Row R
Row T
Row U
Row V
5.2 Pin description
Table 4. Pin description Ball # T4 T1 R3 T2 T3 U1 V1 U2 V3 U3 V2 Type[1] I I I O RV RV RV RV P P P Description analog input channel A analog input channel B analog input to LNA analog output of LNA; connect to AINA or AINB via external capacitor if used ADC common reference voltage and analog output reference voltage combined on-chip ADC reference voltage ADC negative reference voltage ADC positive reference voltage 1.8 V for dual ADC 3.3 V for dual ADC ground for dual ADC Signal name AINA AINB AIN_LNA AOUT_LNA VCOM(DADC) VREF(DADC) VREFN(DADC) VREFP(DADC) VDD(DADC1V8) VDD(DADC3V3) VSS(DADC)
Analog in (dual converter)
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
6 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description ...continued Ball # U7 T7 U6 T6 U5 V10 U10 N3 M2 P3 M3 N2 N1 M1 L2 L1 R1 R2 P2 P1 H17 G16 G17 G18 F16 F17 F18 L17 L18 M18 L16 P17 N17 M17 M16 Type[1] I I I I I P P O O O O O O RV RV P P P P P FI FI FI FO FO FO O I I P P P P P P P Description multiplexed analog input multiplexed analog input multiplexed analog input multiplexed analog input multiplexed analog input 3.3 V analog supply and reference voltage ground amplified analog out, channel A DAC analog out, channel A amplified analog out, channel B DAC analog out, channel B amplified analog return, channel A amplified analog return, channel B negative reference voltage positive reference voltage 3.3 V for DAC 3.3 V for amplifier 3.3 V for amplifier amplifier ground amplifier ground DAI bit clock; 5 V tolerant GPIO pin DAI serial data input; 5 V tolerant GPIO pin DAI word select; 5 V tolerant GPIO pin DAO bit clock; 5 V tolerant GPIO pin 256 x clock output; 5 V tolerant GPIO pin DAO serial data output; 5 V tolerant GPIO pin DAO word select; 5 V tolerant pin DC-to-DC activation DC-to-DC deactivation reference circuit ground, not connected to substrate DC-to-DC main ground and substrate connect to external coil for DC/DC1 connect to external coil for DC/DC2 connect to battery + DC/DC1 3.3 V input voltage DC/DC2 1.8 V output voltage
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Signal name AIN0 AIN1 AIN2 AIN3 AIN4 VDD(ADC3V3) VSS(ADC) AOUTA AOUTA_DAC AOUTB AOUTB_DAC AOUTRA AOUTRB VREFN(DAC) VREFP(DAC) VDD(DAC3V3) VDD1(AMP3V3) VDD2(AMP3V3) VSS1(AMP) VSS2(AMP) DAI interface BCKI/P3[1] DATI/P3[0] WSI/P3[2] DAO interface BCKO/P3[5] DCLKO/P3[3] DATO/P3[6] WSO START STOP DCDC_CLEAN DCDC_GND DCDC_LX1 DCDC_LX2 DCDC_VBAT DCDC_VDDI(3V3)
Analog in (single converter)
Analog out (dual channel)
DC-to-DC converters
DCDC_VDDO(1V8) N18
LPC2880_LPC2888_1
Preliminary data sheet
Rev. 01 -- 22 June 2006
7 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description ...continued Ball # P18 N16 T18 A1 A2 B2 A3 A4 B4 A5 B5 C4 C5 C6 B6 C7 B7 C8 B8 E16 E17 E18 D16 D17 D18 A18 B18 C18 B17 C17 B16 C16 B15 C15 FO address bus for SDRAM and static memory; GPIO pins FI external memory data bus, high byte (I/O); GPIO pins Type[1] P P P P FI Description DC/DC1 3.3 V output voltage ground for DC/DC1, not connected to substrate ground for DC/DC2, not connected to substrate connect to +5 V pin of USB connector external memory data bus, low byte (I/O); GPIO pins
Signal name DCDC_VSS1 DCDC_VSS2 DCDC_VUSB D0/P0[0] D1/P0[1] D2/P0[2] D3/P0[3] D4/P0[4] D5/P0[5] D6/P0[6] D7/P0[7] D8/P0[8] D9/P0[9] D10/P0[10] D11/P0[11] D12/P0[12] D13/P0[13] D14/P0[14] D15/P0[15] A0/P0[16] A1/P0[17] A2/P0[18] A3/P0[19] A4/P0[20] A5/P0[21] A6/P0[22] A7/P0[23] A8/P0[24] A9/P0[25] A10/P0[26] A11/P0[27] A12/P0[28] A13/P0[29] A14/P0[30]
DCDC_VDDO(3V3) R18
External memory interface
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
8 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 4. A15/P0[31] A16/P1[0] A17/P1[1] A18/P1[2] A19/P1[3] A20/P1[4]
Pin description ...continued Ball # A14 B14 C14 A13 B13 C13 A12 B12 C10 B10 C12 A11 B9 A10 A17 A9 B1 C9 A8 B11 C11 K18 J16 K16 K17 interface H16 J17 U4 V4 T5 U12 T13 U13 I/O I/O I I I I I O serial clock (input/open-drain output); 5 V tolerant pin serial data (input/open-drain output); 5 V tolerant pin JTAG selection (pull-down); 5 V tolerant pin JTAG reset input (pull-down); 5 V tolerant pin JTAG data input (pull-up); 5 V tolerant pin JTAG mode select input (pull-up); 5 V tolerant pin JTAG reset input (pull-down); 5 V tolerant pin JTAG data output; 5 V tolerant pin FO FO FO FO FO FO FO FO FO FO FO FO FO FO FO FI FI FI FI byte lane select for D[7:0], active LOW for static memory; GPIO pin byte lane select for D[15:8], active LOW for static memory; GPIO pin column address strobe, active LOW for SDRAM; GPIO pin clock enable; active HIGH for SDRAM; GPIO pin data mask output for D[7:0], active HIGH for SDRAM; GPIO pin data mask output for D[15:8], active HIGH for SDRAM; GPIO pin chip select, active LOW for SDRAM; GPIO pin clock for SDRAM and SyncFlash memory; GPIO pin output enable, active LOW for static memory; GPIO pin row address strobe, active LOW for SDRAM; GPIO pin reset power down, active LOW for SyncFlash memory; GPIO pin chip select, active LOW for static memory bank 0; GPIO pin chip select, active LOW for static memory bank 1; GPIO pin chip select, active LOW for static memory bank 2; GPIO pin write enable, active LOW for SDRAM and static memory; GPIO pin start up MODE PIN1 (pull down); 5 V tolerant GPIO pin start up MODE PIN2 (pull down); 5 V tolerant GPIO pin 5 V tolerant GPIO pin 5 V tolerant GPIO pin Type[1] FO Description address bus for static memory; GPIO pins
Signal name
BLS0/P1[12] BLS1/P1[13] CAS/P1[16] CKE/P1[9] DQM0/P1[10] DQM1/P1[11] DYCS/P1[8] MCLKO/P1[14] OE/P1[18] RAS/P1[17] RPO/P1[19] STCS0/P1[5] STCS1/P1[5] STCS2/P1[5] WE/P1[15] MODE1/P2[2] MODE2/P2[3] P2[0] P2[1] I2C-bus SCL SDA JTAG interface JTAG_SEL JTAG_TCK JTAG_TDI JTAG_TMS JTAG_TRST JTAG_TDO
GPIO and mode control
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
9 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description ...continued Ball # B3 C2 C1 C3 D2 D1 D3 E2 E3 F2 F3 G2 H2 H3 J2 J1 J3 G3 V7 T8 U8 V8 T10 V9 U9 T9 T14 K2 K3 K1 L3 Type[1] FO FO FO FO FO FO FO FO FO FO FO FO FI FI FI FI FI FO I O P P I O P P I FI FI FO FO 6800 E or 8080 RD or 5 V tolerant GPIO pin `high' data register select, `low' instruction register select, or 5 V tolerant GPIO pin 6800 W/R or 8080 WR or 5 V tolerant GPIO pin command (I/O); 5 V tolerant GPIO pin data bus from/to MCI/SD card (I/O); 5 V tolerant GPIO pin data bus from/to MCI/SD card (I/O); 5 V tolerant GPIO pin data bus from/to MCI/SD card (I/O); 5 V tolerant GPIO pin data bus from/to MCI/SD card (I/O); 5 V tolerant GPIO pin MCI clock output; 5 V tolerant GPIO pin 32.768 kHz oscillator input 32.768 kHz oscillator output 1.8 V ground main oscillator input main oscillator output 1.8 V ground master reset, active LOW; 5 V tolerant pin clear to send or transmit flow control, active LOW; 5 V tolerant GPIO pin serial input; 5 V tolerant GPIO pin request to send or receive flow control, active LOW; 5 V tolerant GPIO pin serial output; 5 V tolerant GPIO pin Description chip select to LCD device, programmable polarity; 5 V tolerant GPIO pin data bus to/from LCD (I/O) or 5 V tolerant GPIO pins
Signal name LCD interface LCS/P4[0] LD0/P4[4] LD1/P4[5] LD2/P4[6] LD3/P4[7] LD4/P4[8] LD5/P4[9] LD6/P4[10] LD7/P4[11] LER/P4[3] LRS/P4[1] LRW/P4[2] MCMD/P5[1] MD0/P5[5] MD1/P5[4] MD2/P5[3] MD3/P5[2] MCLK/P5[0] X32I X32O VDD(OSC321V8) VSS(OSC32) Oscillator (main) XTALI XTALO VDD(OSC1V8) VSS(OSC) Reset RESET UART CTS/P6[2] RXD/P6[0] RTS/P6[3] TXD/P6[1]
Memory card interface
Oscillator (32.768 kHz)
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
10 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 4.
Pin description ...continued Ball # T17 U17 U14 T15 P16 U15 U16 U18 V18 R17 R16 T16 H1 V15 A16 E1 V11 A7 V16 V5 V14 J18 G1 A15 T12 F1 V12 A6 U11 V6 V17 T11 V13 H18 Type[1] I/O I/O FI P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Description negative USB data line positive USB data line USB supply detection; 5 V tolerant GPIO pin external 1.5 k resistor to analog ground external 12 k resistor to analog supply voltage (3.3 V) analog 1.8 V analog 1.8 V analog 3.3 V analog 3.3 V analog ground analog ground analog ground 1.8 V for internal RAM and ROM 1.8 V for internal flash memory 1.8 V or 3.3 V for external memory controller 3.3 V for peripherals 1.8 V for core 1.8 V or 3.3 V for external memory controller 1.8 V for internal flash memory 3.3 V for peripherals 3.3 V for peripherals 3.3 V for peripherals ground for internal RAM and ROM ground for external memory controller ground for other internal blocks ground for peripherals ground for core ground for external memory controller ground for other internal blocks ground for peripherals ground for core, substrate, flash ground for other internal blocks ground for peripherals ground for peripherals
Signal name USB interface DM DP VBUS/P7[0] RPU RREF VDD1(USB1V8) VDD2(USB1V8) VDD3(USB3V3) VDD4(USB3V3) VSS1(USB) VSS2(USB) VSS3(USB) VDD1(CORE1V8) VDD1(FLASH1V8) VDD1(EMC) VDD1(IO3V3) VDD2(CORE1V8) VDD2(EMC) VDD2(FLASH1V8) VDD2(IO3V3) VDD3(IO3V3) VDD4(IO3V3) VSS1(CORE) VSS1(EMC) VSS1(INT) VSS1(IO) VSS2(CORE) VSS2(EMC) VSS2(INT) VSS2(IO) VSS3(CORE) VSS3(INT) VSS3(IO) VSS4(IO)
[1]
Digital power and ground
I = input; O = output; I/O = input/output; RV = reference voltage; FI = functional input; FO = functional output; P = power or ground
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
11 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
6. Functional description
6.1 Architectural overview
The LPC2880/LPC2888 includes an ARM7TDMI CPU with an 8 kB cache, an AMBA AHB interfacing to high-speed on-chip peripherals and internal and external memory, and four AMBA APBs for connection to other on-chip peripheral functions. The LPC2880/LPC2888 includes a multi-layer AHB and four separate APBs, in order to minimize interference between the USB controller, other DMA operations, and processor activity. Bus masters include the ARM7 itself, the USB block, and the general purpose DMA controller. Lower speed peripheral functions are connected to the APB buses. The four AHB-to-APB bridges interface the APB buses to the AHB bus.
6.1.1 ARM7TDMI processor
The ARM7TDMI is a general purpose 32-bit microprocessor that offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISCs. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI processor has two instruction sets:
* The standard 32-bit ARM instruction set. * A 16-bit Thumb instruction set.
The Thumb set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide down to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. The ARM7TDMI processor is described in detail on the ARM web site.
6.1.2 On-chip flash memory system
The LPC2880/LPC2888 includes a 1 MB flash memory system. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the USB port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
LPC2880_LPC2888_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
12 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
The flash is 128 bit wide and includes buffering to allow 3 out of 4 sequential read operations to operate without wait states.
6.1.3 On-chip static RAM
The LPC2880/LPC2888 includes 64 kB of static RAM that may be used for code and/or data storage.
6.1.4 On-chip ROM
The LPC2880/LPC2888 includes an on-chip ROM that contains boot code. Execution begins in on-chip ROM after a Reset. The boot code in this ROM reads the state of the mode inputs and accordingly does one of the following: 1. Starts execution in internal flash 2. Starts execution in external memory 3. Performs a hardware self-test, or 4. Downloads code from the USB interface into on-chip RAM and transfers control to the downloaded code
6.2 Memory map
The LPC2880/LPC2888 memory map incorporates several distinct regions, as shown in Figure 3. When an application is running, the CPU interrupt vectors are remapped to allow them to reside in on-chip SRAM.
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16/32-bit ARM microcontrollers with external memory interface
4.0 GB reserved 0x9000 0000 to 0xFFFF FFFF
0xFFFF FFFF 0x9000 0000 0x8FFF FFFF
peripherals 2.0 GB
includes AHB and 4 APB buses reserved dynamic memory bank 0, 64 MB reserved static memory bank 2, 2 MB
0x8000 0000 to 0x8FFF FFFF 0x5400 0000 to 0x7FFF FFFF 0x5000 0000 to 0x53FF FFFF 0x4820 0000 to 0x4FFF FFFF 0x4800 0000 to 0x481F FFFF 0x4420 0000 to 0x47FF FFFF 0x4400 0000 to 0x441F FFFF 0x4020 0000 to 0x43FF FFFF 0x4000 0000 to 0x401F FFFF 0x3400 0000 to 0x3FFF FFFF 0x3000 0000 to 0x33FF FFFF 0x2820 0000 to 0x2FFF FFFF 0x2800 0000 to 0x281F FFFF 0x2420 0000 to 0x27FF FFFF 0x2400 0000 to 0x241F FFFF 0x2020 0000 to 0x23FF FFFF 0x2000 0000 to 0x201F FFFF 0x1050 0000 to 0x1FFF FFFF 0x1040 0000 to 0x104F FFFF 0x1000 0000 to 0x0000 003F 0x0050 0000 to 0x0FFF FFFF 0x0040 0000 to 0x0040 FFFF 0x2000 0000 0x1FFF FFFF 0x4000 0000 0x3FFF FFFF 0x8000 0000 0x7FFF FFFF
external memory (second instance)
reserved static memory bank 1, 2 MB reserved static memory bank 0, 2 MB
1.0 GB reserved dynamic memory bank 0, 64 MB reserved static memory bank 2, 2 MB external memory (first instance) reserved static memory bank 1, 2 MB reserved static memory bank 0, 2 MB reserved internal memory internal flash (1 MB) reserved reserved internal RAM (64 kB) remapped area internal ROM (32 kB) exception vectors 0x0020 0000 to 0x0020 7FFF 0x0000 0000 to 0x0000 001F
0x1000 0000 0x0FFF FFFF
0.0 GB
0x0000 0000
002aac240
Fig 3. Memory map
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16/32-bit ARM microcontrollers with external memory interface
6.3 Cache
The CPU of the LPC2880/LPC2888 has been extended with a 2-way set-associative cache controller. The cache is 8 kB in size and can store both data and instruction code. If code that is being executed is present in the cache from a previous execution, the CPU will not experience code fetch waits. Similarly, if requested data is present in the cache, the CPU will not experience a data access wait. The trade-off of introducing this cache is that each AHB access that bypasses the cache will have an extra wait state inserted. Therefore it is advisable to enable instruction caching (and preferably data caching as well) for all memories, to provide the highest performance.
6.3.1 Cache operation
This cache works as follows, for each page of which the cache is enabled:
* If a read is requested and the information is not in the cache (a cache miss), a line of
eight 32-bit words will be read from the AHB bus. The CPU waits until this process is complete.
* If a read is requested and the information is found in the cache (a cache hit), the
information is read from cache, with zero wait states.
* If data is written, and the location is not in the cache (a cache miss), the data will be
written directly to memory.
* If data is written, and the location is in the cache, because this location has been read
before (a cache hit), then data is written into the cache with zero wait states and the cache line is marked as `dirty'.
* If a `dirty' cache line is about to be discarded because of a cache miss on a read
request, this line will first be written back to memory (a cache-line flush). The cache can be set to data-only, instruction-only or combined (unified) caching. The cache has 16 configurable pages, each 2 MB in range. The pages occupy the bottom 32 MB of the memory map. The virtual address and enable/disable status is configurable for each page.
6.3.2 Features
* * * *
8 kB, 2-way set-associative cache. May be used as both an instruction and data cache. Zero wait states for a cache hit. 16 configurable pages, each 2 MB in range.
6.4 Flash memory and programming
The LPC2888 incorporates 1 MB flash memory system, while the LPC2880 is a flash-less device. The flash memory of the LPC2888 may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the USB port. The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage, field firmware upgrades, etc.
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16/32-bit ARM microcontrollers with external memory interface
Programming the flash in a running application is accomplished via a register interface on the APB bus. The flash module can generate an interrupt request when burning or erasing is completed. The flash memory contains a buffer to allow for faster execution. Information is read from the flash 128 bits at a time. The buffer holds this entire amount, which can represent four 32-bit ARM instructions. These captured instructions can them be executed without flash read delays, improving system performance.
6.4.1 Features
* Flash access for processor execution and data read is via the AHB bus. * Flash programming in a running application is via an APB register interface. * Initial programming or reprogramming is can be accomplished from the USB port. 6.5 External memory controller
The LPC2880/LPC2888 External Memory Controller (EMC) is a multi-port memory controller that supports asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as Single Data Rate SDRAM. It complies with ARM's AMBA.
6.5.1 Features
* Dynamic memory interface support including Single Data Rate SDRAM. * Asynchronous static memory device support including RAM, ROM, and flash, with or
without asynchronous page mode.
* * * * *
Low transaction latency. Read and write buffers to reduce latency and to improve performance. 8-bit and 16-bit static memory support. 16-bit SDRAM memory support. Static memory features include: - Asynchronous page mode read. - Programmable wait states. - Bus turnaround delay. - Output enable, and write enable delays. - Extended wait. - 2 MB address range with three chip selects.
* One chip select for synchronous memory and three chip selects for static memory
devices.
* Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. * Dynamic memory self-refresh mode controlled by software. * Controller supports 2 k, 4 k, and 8 k row address synchronous memory parts. That is
typically 512 MB, 256 MB, and 128 MB parts, with 4, 8, or 16 data lines per device. Note: Synchronous static memory devices (synchronous burst mode) are not supported.
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16/32-bit ARM microcontrollers with external memory interface
6.6 GPIO
Many device pins that are not connected to a specific peripheral function can be used as are GPIOs. These pins can be controlled by the MODE registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The current state of the port pins may be read back via the PIN registers.
6.6.1 Features
* 81 pins have dual use as a specific function I/O or as a GPIO. * Each dual use pin can be programmed for functional I/O, drive high, drive low, or
hi-Z/input.
* Four pins are dedicated as GPIO, programmable for drive high, drive low, or
hi-Z/input.
6.7 Interrupt controller
The interrupt controller accepts all of the interrupt request inputs and categorizes them as FIQ or IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQ has the highest priority. If more than one request is assigned to FIQ, the interrupt controller combines the requests to produce the FIQ signal to the ARM processor. The interrupt controller combines the requests from all the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the interrupt controller and jumping there.
6.7.1 Features
* * * * *
Maps all LPC2880/LPC2888 interrupt sources to processor FIQ and IRQ Level sensitive sources Programmable priority among sources Nested interrupt capability Software interrupt capability for each source
6.8 Event router
105 external and internal LPC2880/LPC2888 signals are connected to the Event Router block. Most of them are device pins, plus a selection of internal signals from other LPC2880/LPC2888 modules. GPIO input pins, functional input pins, and even functional outputs can be monitored by the Event Router. Each signal can act as an interrupt source, or a clock enable or reset source for LPC2880/LPC2888 modules, with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity. The outputs of the polarity and sensitivity logic can be read from Raw Status Registers 0 to 3. Each active state is next masked/enabled by a "global" mask bit for that signal. The results can be read from Pending Registers 0 to 3.
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16/32-bit ARM microcontrollers with external memory interface
All 105 Pending signals are presented to each of the five output logic blocks. Each output logic block includes a set of four Interrupt Output Mask Registers, each set totalling 105 bits, that control whether each signal applies to that output. These are logically ANDed with the corresponding Pending signals, and the 105 results in each logic block are logically ORed to make the output of the block. The 525 results can be read in the Interrupt Output Pending Registers. Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it can serve as a wake-up generator. The five outputs can be read in the Output Register.
6.9 General purpose timers
The LPC2880/LPC2888 contains two fully independent general purpose timers. Each timer is a 32-bit wide down counter with selectable prescaler. The prescaler allows either the system clock to be used directly, or the clock to be divided by 16 or 256. Two modes of operation are available, free-running and periodic timer. In periodic timer mode, the counter will generate an interrupt at a constant interval. In free-running mode the timer will overflow after reaching its zero value and continue to count down from the maximum value.
6.9.1 Features
* Two independent 32-bit timers. * Free-running or periodic operating modes. * Generate timed interrupts. 6.10 Watchdog timer
The purpose of the Watchdog Timer is to interrupt and/or reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate an interrupt or a system reset if the user program fails to reset the Watchdog within a predetermined amount of time. Alternatively, it can be used as an additional general purpose Timer. The WDT clock increments a 32-bit Prescale Counter, the value of which is continually compared to the value of the Prescale Register. When the Prescale Counter matches the Prescale Register at a WDT clock edge, the Prescale Counter is cleared and the 32-bit Timer Counter is incremented. Thus the Prescale facility divides the WDT clock by the value in the Prescale Register plus one. The value of the Timer Counter is continually compared to the values in two registers called Match Register 0 and 1. When/if the value of the Timer Counter matches that of Match Register 0 at a WDT clock edge, a signal `m0' can be asserted to the Event Router, which can be programmed to send an interrupt signal to the Interrupt Controller as a result. When/if the value of the Timer Counter matches that of Match Register 1 at a WDT clock edge, a signal `m1' can be asserted to the CGU, which resets the chip as a result. The CGU also includes a flag to indicate whether a reset is due to a Watchdog time-out.
6.10.1 Features
* Optionally resets chip (via Clock Generation Unit) if not periodically reloaded.
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16/32-bit ARM microcontrollers with external memory interface
* Optional interrupt via Event Router. * 32-bit Prescaler and 32-bit Counter allow extended watchdog period. 6.11 Real-time clock
The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in either mode.
6.11.1 Features
* Measures the passage of time to maintain a calendar and clock. * Ultra Low Power design to support battery powered systems. * Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day
of Year.
* Dedicated 32 kHz oscillator. * Dedicated power supply pin can be connected to a battery or to the main 1.8 V. 6.12 General purpose DMA controller
The General Purpose DMA Controller (GPDMA) is an AMBA AHB compliant master allowing selected LPC2880/LPC2888 peripherals to have DMA support. Peripherals that can be serviced by the GPDMA channels include the MCI/SD card interface, UART TX and/or RX, the I2C-bus interface, the Simple Analog Out (SAO) front-ends to the I2S/DAO and 16-bit dual DACs, the Simple Analog In (SAI) interfaces for data from the I2S/DAI and 16-bit dual ADCs, and the output to the LCD interface.
6.12.1 Features
* Eight DMA channels. Each channel can support a unidirectional transfer, or a pair of
channels can be used together to follow a linked list of buffer addresses and transfer counts. The GPDMA provides 16 peripheral DMA request lines. Most of these are connected to the peripherals listed above; two can be used for external requests.
* The GPDMA supports a subset of the flow control signals supported by ARM DMA
channels, specifically `single' but not `burst' operation.
* Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and
peripheral-to-peripheral transfers.
* Scatter or gather DMA is supported through the use of linked lists. This means that
the source and destination areas do not have to occupy contiguous areas of memory.
* Rotating channel priority. Each DMA channel has equal opportunity to perform
transfers.
* The GPDMA is one of three AHB masters in the LPC2880/LPC2888, the others being
the ARM7 processor and the USB interface.
* Incrementing or non-incrementing addressing for source and destination. * Supports 8-bit, 16-bit, and 32-bit wide transactions. * GPDMA channels can be programmed to swap data between big- and little-endian
formats during a transfer.
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16/32-bit ARM microcontrollers with external memory interface
* An interrupt to the processor can be generated on DMA completion, when a DMA
channel is halfway to completion, or when a DMA error has occurred.
6.13 UART and IrDA
The LPC2880/LPC2888 contains one UART with baud rate generator and IrDA support.
6.13.1 Features
* * * * * * * *
32-B Receive and Transmit FIFOs. Register locations conform to the 16C650 industry standard. Receiver FIFO trigger points at 1 B, 16 B, 24 B, and 28 B. Built-in baud rate generator. CGU generates UART clock including fractional divider capability. Auto baud capability. Optional hardware flow control. IrDA mode for infrared communication.
6.14 I2C-bus interface
The LPC2880/LPC2888 I2C-bus interface is byte oriented and has four operating modes: master Transmit mode, master Receive mode, slave Transmit mode and slave Receive mode. The interface complies with the entire I2C-bus specification, and allows turning power off to the LPC2880/LPC2888 without causing a problem with other devices on the same I2C-bus.
6.14.1 Features
* Standard I2C-bus interface, configurable as Master, Slave, or Master/Slave. * Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
* Programmable clock allows adjustment of I2C-bus transfer rates. * Bidirectional data transfer between masters and slaves. * Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
* Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
* Supports normal (100 kHz) and fast (400 kHz) operation. 6.15 10-bit A/D converter
The LPC2880/LPC2888 contains a single 10-bit successive approximation analog to digital converter with five multiplexed channels.
6.15.1 Features
* 10-bit successive approximation analog to digital converter. * Input multiplexing among 5 pins.
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16/32-bit ARM microcontrollers with external memory interface
* * * *
Power-down mode. Measurement range 0 V to 3.3 V. 10-bit conversion time 2.44 s. Single or continuous conversion mode.
6.16 Analog I/O
The analog I/O system includes an I2S input channel, an I2S output channel, a dual A/D converter, and a dual D/A converter. Each channel includes a separate 4 sample FIFO. Each of the two ADC inputs includes a Programmable Gain Amplifier (PGA). A separate input, which can be routed to either ADC, also include an additional Low Noise Amplifier (LNA). Each DAC has associated pins for unbuffered and amplified outputs.
6.16.1 Features
* I2S-bus input channel with a 4 sample FIFO for stereo Digital Analog Input (DAI). * I2S-bus output channel with a 4 sample FIFO for stereo Digital Analog Output (DAO). * Dual 16-bit A/D converters with individual inputs routed through programmable gain
amplifiers. Each ADC can alternatively take its input from a single pin that includes an additional low noise amplifier. Input takes place through a 4 sample FIFO.
* Dual 16-bit D/A converters. Each DAC includes both a direct output and an amplified
output. Output takes place through a 4 sample FIFO.
6.17 USB 2.0 high-speed device controller
The USB is a 4 wire bus that supports communication between a host and a number (127 max.) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, un-plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The host schedules transactions in 1 ms frames. Each frame contains an SoF marker and transactions that transfer data to/from device endpoints. Each device can have a maximum of 16 logical or 32 physical endpoints. There are 4 types of transfers defined for the endpoints. Control transfers are used to configure the device. Interrupt transfers are used for periodic data transfer. Bulk transfers are used when rate of transfer is not critical. Isochronous transfers have guaranteed delivery time but no error correction. The LPC2880/LPC2888 USB controller enables 480 Mbit/s or 12 Mbit/s data exchange with a USB host controller. It includes a USB controller, a DMA engine, and a USB 2.0 ATX physical interface. The USB controller consists of the protocol engine and buffer management blocks. It includes an SRAM that is accessible to the DMA engine and to the processor via the register interface. The DMA engine is an AHB master, having direct access to all ARM memory space but particularly to on-chip RAM. Each USB endpoint that requires its data to be transferred via DMA is allocated to a logical DMA channel in the DMA engine.
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Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Endpoints with small packet sizes can be handled by software via registers in the USB controller. In particular, Control Endpoint 0 is always handled in this way.
6.17.1 Features
* * * * * * * * * *
Fully compliant with USB 2.0 specification (HS and FS). 16 physical endpoints. Supports Control, Bulk, Interrupt and Isochronous endpoints. Endpoint type selection by software Endpoint maximum packet size setting by software Supports Soft Connect feature (requires an external 1.5 k resistor connected to the USB_RPU pad). Supports bus-powered capability with low suspend current. Four Read/Write DMA channels. Supports Burst data transfers on the AHB. Supports Retry and Split transactions on the AHB.
6.18 SD/MMC card interface
The Secure Digital and Multimedia Card Interface (MCI) is an interface between the Advanced Peripheral Bus (APB) system bus and multimedia and/or secure digital memory cards. The interface provides all functions specific to the Secure Digital/MultiMedia memory card, such as the clock generation unit, power management control, command, data transfer, interrupt generation, and DMA request generation.
6.18.1 Features
* Conformance to Multimedia Card Specification v2.11. * Conformance to Secure Digital Memory Card Physical Layer Specification, v0.96. * Use as a multimedia card bus or a secure digital memory card bus host. It can be
connected to several multimedia cards, or a single secure digital memory card.
* DMA transfers are supported through the Simple DMA facility. 6.19 LCD interface
The LCD interface contains logic to interface to a 6800 or 8080 bus compatible LCD controller. The LCD interface is compatible with the 6800 bus standard and the 8080 bus standard, with one address pin (RS) for selecting the data or instruction register. The LCD interface makes use of a configurable clock (programmed in the CGU) to adjust the speed of the 6800/8080 bus to the speed of the connected peripheral.
6.19.1 Features
* 8-bit or 4-bit parallel interface mode: 6800-series, 8080-series. * Supports multiple frequencies for the bus, to support high and low speed LCD
controllers.
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16/32-bit ARM microcontrollers with external memory interface
* * * *
Supports polling the busy flag from the LCD controller to avoid CPU polling. Contains a 16 B FIFO for sending control and data information to the LCD controller. Contains a serial interface which uses the same FIFO for serial transmissions. Supports FIFO level flow control to the General Purpose DMA controller.
6.20 Clocking and power control
Clocking in the LPC2880/LPC2888 is controlled by a versatile Clock Generation Unit (CGU), so that system and peripheral requirements may be met, while allowing optimization of power consumption. Clocks to most functions may be turned off if not needed, and may be enabled and disabled by selected events through the Event Router. Clock sources include a high frequency (1 MHz to 20 MHz) crystal oscillator and a 32 kHz RTC oscillator. Higher frequency clocks may be generated through the use of two programmable PLLs. Reset of individual functional blocks is also controlled by the CGU. Full chip reset can be initiated by the external reset pin or by the watchdog timer.
6.20.1 Features
* Power and performance control provided by versatile clock generation to individual
functional blocks.
* * * *
Multiple clock sources including external crystal and programmable PLLs. Watchdog timer to monitor software integrity. Individual control of software reset to many functional blocks. Lower speed peripherals are connected to an APB bus for lower power consumption.
6.20.2 Reset
The LPC2880/LPC2888 has two sources of reset: the RESET_N pin and the watchdog reset. The RESET pin includes an on-chip pull-up. The RESET_N pin must remain asserted at power-up for 1 ms after power supply voltages are stable. This includes on-chip DC-to-DC converter voltages. When a chip reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The on-chip watchdog timer can cause a chip reset if not updated within a user programmable amount of time. A status register allows software to determine if a chip reset was caused by the watchdog timer. The watchdog timer can also be configured to generate an interrupt if desired. Software reset of many individual functional blocks may be performed via registers within the CGU.
6.20.3 Crystal oscillator
The main oscillator is the basis for the clocks most chip functions use by default. The oscillator may be used with crystal frequencies from 1 MHz to 20 MHz.
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16/32-bit ARM microcontrollers with external memory interface
6.20.4 PLLs
The LPC2880/LPC2888 includes two PLLs: a low power PLL that may be used to provide clocks to most chip functions; a high-speed PLL that may be used to generate faster clocks for selected chip functions, if needed. Each PLL can be driven from several clock sources. These include the main oscillator (1 MHz to 20 MHz), the RTC oscillator (32 kHz), the bit clock or word select inputs of the I2S input channel, the clock input from the SD/MMC Card interface, or the output clock from the other PLL. The low power PLL takes the input clock and multiplies it up to a higher frequency (by 1 to 32), then divides it down (by 1, 2, 4, or 8) to provide the output clock used by the CGU. The output frequency of this PLL can range from 9.75 MHz to 160 MHz. Functional blocks may have limitations below this upper limit. The high-speed PLL takes the input clock, optionally divides it down (by 1 to 256), then multiplies it up to a higher frequency (by 1 to 1024), then divides it down (by 1 to 16) to provide the output clock used by the CGU. The output frequency of this PLL can range from 17 MHz to 550 MHz. Functional blocks may have limitations below this upper limit.
6.20.5 Power control and modes
Power control on the LPC2880/LPC2888 is accomplished by detailed control over the clocking of each functional block via the CGU. The LPC2880/LPC2888 includes a very versatile clocking scheme that provides a great deal of control over performance and power usage. On-chip functions are divided into 11 groups. Each group has a selection for one of several basic clock sources. Graceful (glitch-free) switching between these clock sources is provided. Three of these functional groups include a fractional divider that allows any rate below the selected clock to be derived. Three other functional groups include more than one fractional divider (up to six), allowing several different clock rates to be generated within the group. Each function within the group can then be assigned to use any one of the generated clocks. Each function within any group can also be individually turned off by disabling the clock to that function. When added to the versatile clock rate selection, this allows very detailed control of power utilization. Each function also can be configured to have clocks automatically turned on and off based on a signal from the Event Router.
6.20.6 APB bus
Many peripheral functions are accessed by on-chip APB buses that are attached to the higher speed AHB bus. The APB bus performs reads and writes to peripheral registers in three peripheral clocks.
6.21 Emulation and debugging
The LPC2880/LPC2888 supports emulation via a dedicated JTAG serial port. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application.
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LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. The EmbeddedICE protocol converter converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core.
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16/32-bit ARM microcontrollers with external memory interface
7. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(1V8) VDD(3V3) VDD(EMC) VIA VI IDD ISS Tstg Ptot(pack) Parameter supply voltage (1.8 V) supply voltage (3.3 V) external memory controller supply voltage analog input voltage input voltage supply current ground current storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model all pins machine model all pins
[1]
[9] [8] [2][3][4] [2][3][5] [6] [7]
Conditions
Min -0.5 -0.5
Max +1.95 +3.6 +1.95 +3.6 VVDD(ADC3V3) +5.0 +3.6 +125
Unit V V V V V V V mA mA C W
in 1.8 V range in 3.3 V range
-0.5 -0.5 -0.5 -0.5 -0.5 -40 -
Vesd
electrostatic discharge voltage
-2000 -200
+2000 +200
V V
The following applies to Table 5: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. All inputs are 5 V tolerant except external memory bus and USB pins. Including voltage on outputs in 3-state mode. 5 V tolerant pins Other I/O pins. Per supply pin. Per ground pin. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. Machine model: equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 series resistor.
[2] [3] [4] [5] [6] [7] [8] [9]
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Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
8. Static characteristics
Table 6. Static characteristics Ta = -40 C to +85 C, unless otherwise specified. Symbol VDD(1V8) VDD(3V3) VDDA(3V3) VDD(EMC) Parameter supply voltage (1.8 V) supply voltage (3.3 V) analog supply voltage (3.3 V) external memory controller supply voltage in 1.8 V range in 3.3 V range VI = 0 V; no pull-up VI = VDD; no pull-down VO = 0 V; VO = VDD; no pull-up/down -(1.5VDD) < VI < (1.5VDD)
[6] [6]
Conditions
[2] [3] [4] [5] [5]
Min 1.7 3 3 1.7 2.7 0.9 0 1.6 2.0 -
Typ[1] 1.8 3.3 3.3 1.8 3.3 1.2 -
Max 1.95 3.6 3.6 1.95 3.6 1.6 3 3 3 100 VDD 0.6 0.8 0.4 0.4 10 10 400 <1 -
Unit V V V V V V A A A mA V V V V V V V V V mA mA mA mA mA mA mA mA A A A A A A mA A
VDCDC_VBAT voltage on pin DCDC_VBAT IIL IIH IOZ Ilatch VI VIH VIL VOH VOL IOH IOL IOHS IOLS IDD(CORE) IDD(EMC) IBAT ICC(osc) IDD(RTC) IDD(ADC) IDDIA LOW-state input current HIGH-state input current OFF-state output current I/O latch-up current input voltage HIGH-state input voltage LOW-state input voltage HIGH-state output voltage LOW-state output voltage HIGH-state output current LOW-state output current HIGH-state short-circuit output current LOW-state short-circuit output current core supply current external memory controller supply current battery supply current oscillator supply current RTC supply current ADC supply current analog input supply current IOH = -1 mA IOH = -4 mA IOL = 4 mA IOL = 4 mA VOH = VDD - 0.4 V VOL = 0.4 V VOH = 0 V VOL = VDD VDD = 1.8 V VDD(EMC) = 1.8 V VDD(EMC) = 3.3 V VDCDC_VBAT = 1.2 V oscillator running oscillator powered down oscillator running oscillator powered down normal powered down normal powered down
[17] [16] [15] [14]
[6] [6][7][8] [9] [10] [9] [10] [9][11] [10][11] [9][11] [10][11] [6][11] [6][11] [12]
VDD - 0.4 VDD - 0.4 -4 4 -45 45 60 300 300
[6][12]
[13]
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
27 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
Table 6. Static characteristics ...continued Ta = -40 C to +85 C, unless otherwise specified. Symbol IDDO(DAC) IDDOA Parameter DAC output supply current analog output supply current Conditions normal powered down normal powered down
[1] [2] [3] [4] [5] [6] [7] [8] [9]
[18] [18] [19] [19]
Min -
Typ[1]
Max -
Unit mA A mA A
Typical ratings are not guaranteed. The values listed are at room temperature (+25 C), nominal supply voltages. Applies to pins VDD1(CORE1V8), VDD2(CORE1V8), VDD1(FLASH1V8), VDD2(FLASH1V8), VDD(OSC1V8), VDD(OSC321V8), VDD1(USB1V8), VDD2(USB1V8). External supply voltage; applies to pins VDD3(USB3V3), VDD4(USB3V3), VDD1(IO3V3), VDD2(IO3V3), VDD3(IO3V3), VDD4(IO3V3). Applies to pins VDD(DADC3V3), VDD(ADC3V3), VDD(DAC3V3), VDD1(AMP3V3), VDD2(AMP3V3). External supply voltage; applies to pins VDD1(EMC), VDD2(EMC). Referenced to the applicable VDD for the pin. Including voltage on outputs in 3-state mode. The applicable VDD voltage for the pin must be present. 1.8 V inputs.
[10] 3.3 V inputs. [11] Accounts for 100 mV voltage drop in all supply lines. [12] Only allowed for a short time period. [13] Applies to pins VDD1(CORE1V8), VDD2(CORE1V8), VDD1(FLASH1V8), VDD2(FLASH1V8) [14] Applies to pin VDD(OSC1V8). [15] Applies to pin VDD(OSC321V8). [16] Applies to pin VDD(ADC3V3). [17] Applies to pins VDD(DADC1V8), VDD(DADC3V3). [18] Applies to pin VDD(DAC3V3). [19] Applies to pins VDD1(AMP3V3), VDD2(AMP3V3).
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
28 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
9. Dynamic characteristics
Table 7. Dynamic characteristics Ta= -40 C to +85 C, unless otherwise specified.[1] Symbol External clock fext Port pins tr tf
[1] [2]
Parameter external clock frequency rise time fall time
Conditions
[2]
Min 1 -
Typ 12 5 5
Max 20 -
Unit MHz ns ns
Parameters are valid over operating temperature range unless otherwise specified. Supplied by an external crystal.
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
29 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
10. Package outline
TFBGA180: plastic thin fine-pitch ball grid array package; 180 balls; body 10 x 10 x 0.8 mm SOT640-1
D
B
A
ball A1 index area A2
E
A
A1
detail X
C e1 e V U T R P N M L K J H G F E D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 11 13 15 17 10 12 14 16 18 X
1/2 e 1/2 e v M C A B w M C
b
y1 C
y
e
e2
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.11 A1 0.31 0.19 A2 0.84 0.76 b 0.39 0.29 D 10.1 9.9 E 10.1 9.9 e 0.5 e1 8.5 e2 8.5 v 0.1 w 0.15 y 0.12 y1 0.1
OUTLINE VERSION SOT640-1
REFERENCES IEC JEDEC MO-195 JEITA
EUROPEAN PROJECTION
ISSUE DATE 01-06-07 03-03-03
Fig 4. Package outline SOT640-1 (TFBGA180)
LPC2880_LPC2888_1 (c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
30 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
11. Abbreviations
Table 8. Acronym ADC AMBA AHB APB CISC CGU DAC DMA FIQ GPIO IrDA IRQ LCD PLL RISC SD/MMC SDRAM SRAM UART USB Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced High-performance Bus Advanced Peripheral Bus Complex Instruction Set Computer Clock Generation Unit Digital-to-Analog Converter Direct Memory Access Fast Interrupt Request General Purpose Input/Output Infrared Data Association Interrupt Request Liquid Crystal Display Phase-Locked Loop Reduced Instruction Set Computer Secure Digital/MultiMedia Card Synchronous Dynamic Random Access Memory Static Random Access Memory Universal Asynchronous Receiver/Transmitter Universal Serial Bus
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
31 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
12. Revision history
Table 9. Revision history Release date 20060622 Data sheet status Preliminary data sheet Change notice Supersedes Document ID LPC2880_LPC2888_1
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
32 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
13. Legal information
13.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.semiconductors.philips.com.
13.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Philips Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Philips Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
to result in personal injury, death or severe property or environmental damage. Philips Semiconductors accepts no liability for inclusion and/or use of Philips Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
13.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, Philips Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- Philips Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- Philips Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a Philips Semiconductors product can reasonably be expected
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of Koninklijke Philips Electronics N.V.
14. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
LPC2880_LPC2888_1
(c) Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Preliminary data sheet
Rev. 01 -- 22 June 2006
33 of 34
Philips Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
15. Contents
1 2 2.1 3 3.1 4 5 5.1 5.2 6 6.1 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.5 6.5.1 6.6 6.6.1 6.7 6.7.1 6.8 6.9 6.9.1 6.10 6.10.1 6.11 6.11.1 6.12 6.12.1 6.13 6.13.1 6.14 6.14.1 6.15 6.15.1 6.16 6.16.1 6.17 6.17.1 6.18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . 12 Architectural overview. . . . . . . . . . . . . . . . . . . 12 ARM7TDMI processor . . . . . . . . . . . . . . . . . . 12 On-chip flash memory system . . . . . . . . . . . . 12 On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13 On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 13 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 13 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Cache operation . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Flash memory and programming . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External memory controller. . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 GPIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General purpose timers . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Real-time clock . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General purpose DMA controller . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 UART and IrDA . . . . . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10-bit A/D converter . . . . . . . . . . . . . . . . . . . . 20 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Analog I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 USB 2.0 high-speed device controller . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SD/MMC card interface . . . . . . . . . . . . . . . . . 22 6.18.1 6.19 6.19.1 6.20 6.20.1 6.20.2 6.20.3 6.20.4 6.20.5 6.20.6 6.21 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LCD interface . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clocking and power control . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power control and modes. . . . . . . . . . . . . . . . APB bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Emulation and debugging. . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 22 22 23 23 23 23 24 24 24 24 26 27 29 30 31 32 33 33 33 33 33 33 34
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) Koninklijke Philips Electronics N.V. 2006.
All rights reserved.
For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: sales.addresses@www.semiconductors.philips.com. Date of release: 22 June 2006 Document identifier: LPC2880_LPC2888_1

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